Biblioteka Cyfrowa
Opis wydania
Challenges for 10 nm MOSFET process integration, Journal of Telecommunications and Information Technology, 2007, nr 2
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Opis :
An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. The need for high-k gate dielectrics and a metal gate electrode is discussed. Different techniques for strain-enhanced mobility are discussed. As an example, ultra thin body SOI devices with high mobility SiGe channels are demonstrated.
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